ECET 230 ECET230 ECET/230 -All Homeworks Weeks 1-7

ECET 230 ECET230 ECET/230 -All Homeworks Weeks 1-7
Week 1
1. Develop the Boolean equation for the circuit shown below
2. Determine the output Y in Problem 1 for the input values shown below
3. Redraw the circuit in Problem 1 using only 2-input NAND gates
4.Develop the Boolean equation for the circuit shown below
5.Determine the period of a clock waveform whose frequency is:
6.Write the VHDL text file (Entity and Architecture) for a 2-input NAND gate.
7. Write the VHDL text file for a 3-input NOR gate.
8.Write the VHDL text file for the circuit shown below
9.Develop the look-up-table (LUT) for the circuit shown in Problem 8.
10. Develop the look-up table for the Boolean equation:
Week 2
1. When a HIGH is on the output of the decoding circuit below, what is the binary code appearing on the inputs?
2. Write the Boolean equations for each of the following codes if an active-LOW decoder output is required:
3. Write the VHDL text file for a 3-to-8 decoder.
4. A 7-segment decoder/driver drives the display below. Using the waveforms shown, determine the sequence of digits that appear on the display.
5. Construct a truth table for an active-LOW output BCD (1-of-10) decoder
6. Derive the truth table for the Y output in the diagram below.
7. Derive the Boolean equation for the Y output in Problem
8.For the multiplexer shown below, determine the output for the following input state:
9. Determine the function of the circuit shown below.
Week 3
1.Determine the decimal value of each of the following unsigned binary numbers:
2.Determine the decimal value of each of the following signed binary number displayed in the 2’s complement form:
3. Determine the outputs (Cout, Sout) of a full-adder for each of the following inputs:
4.The circuit below is an attempt to build a half-adder. Will the Cout and Sout function properly? Demonstrate your rationale.
5.Determine the outputs for the circuit shown below. Assume that C0 = 0 for all cases.
6.Write the VHDL text for the 2-bit magnitude comparator shown below.
7.Write the VHDL text file for a 2-bit full-adder using BIT types.
8.Write the VHDL text file for a 2-bit full-adder using INTEGER types.
9.Develop the VHDL text file for a 4 state, 8-bit arithmetic and logic unit (ALU). The ALU inputs 2 8-bit numbers (A and B) and output an 8-bit result (Y) as shown in the table. (2 points).
10. Write the VHDL text file for the circuit shown in Problem 9
Week 4
1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW.
2. Sketch the Q output for the waveforms shown. Assume that Q starts LOW.
3. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
4. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
5. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
6. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
7. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
8. Using Quartus II, or an equivalent VHDL entry program, model the D flip-flop shown below. Attach the simulation file.
9. Using Quartus II, or an equivalent VHDL entry program, model the J-K flip-flop shown below. Attach the simulation file.
Week 5
1.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the circuit below. Attach the .vhd and simulation files.
2.What is the output frequency of Q1 in the circuit shown below?
3.A synchronous binary counter is used to divide a 1 MHz input frequency to 3.90625 kHz. What is the MOD number of the counter and how many flip-flops are required?
4. If the MOD-8 binary counter is driven by a 10 MHz input clock with a 5% duty cycle, what is the output frequency and duty cycle of the final stage?
5.Determine the output frequency for the cascaded counter configuration shown below.
6.Determine the count sequence for the counter shown below.
7. Write the VHDL text file for a MOD-1024 counter using INTEGER types
8.Develop the state diagram for a MOD-5 counter with the following count sequence:
000, 001, 010, 110, 111, 000, etc. All undefined states must return to 000.
Week 6
1.The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses, the register contains:
(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101
2. With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in:
(a) 80 ms (b) 8 ms (c) 80 ms (d) 10 ms
3. For a 10-bit serial-in/serial-out shift register, determine Data out for the Data in and clock waveforms shown below. Assume that the register is initially cleared.
4. Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the shift register specified in Problem 3. Verify the timing diagram shown in Problem 3. Attach the .vhd and simulation files.
5.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the 74LS194A universal, bi-directional shift register. Attach the .vhd and simulation files.
6.In your own words, explain the purpose of concatenation in a VHDL signal assignment.
7. Develop the state diagram for a MOD-4 counter with an even number count sequence: 000, 010, 100, 110, 000, etc. All undefined states must return to 000.
Week 7
1. Is the state machine below a Moore machine or a Mealy machine? Explain your rationale.
3. Using the state diagram in Figure 10.44 on page 663 of the Dueck textbook, briefly explain the operation of the circuit shown.
4.Create the VHDL text file for the state machine described in Problem 3.
5. Create the Quartus II simulation for the state machine shown in Problem 3.
6. Using the state diagram in Figure 10.46 on page 665 of the Dueck textbook, how many state variables are required to implement this state machine? Why?
7. List the unused states for Problem 6?
8. Create the VHDL text file for the state machine described in Problem 6.
9. Why do we need to specify unused states in the text file in Problem 8?
10. Create the Quartus II simulation for the state machine shown in Problem 6.